Technical Papers
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Implementation-Quality Prototyping With Olympus-SoCTM: Accelerating Design Closure for Advanced ICs
The growing complexity of today’s ICs and tight market schedules are driving a demand for more powerful solutions for design prototyping. Prototyping helps designers determine the feasibility of implementing a particular design given the various requirements. By using Olympus-SoC for rapid prototyping early in the design cycle, designers can catch issues with macro placement, missing constraints, RTL problems, and many other design problems. In this paper, we show how design prototyping with the Mentor Graphics Olympus-SoC physical implementation system improves predictability and facilitates design closure.
Confronting Chip Assembly Challenges: Avoid Late-Stage Bottlenecks in Physical Design
The increasing size and complexity of today’s multi-million gate SoCs necessitates hierarchical chip design methodologies, which partition the chip into smaller pieces. A hierarchical methodology is necessary for large SoCs because it extends the capacity of design-automation tools, improves tool runtimes, and limits last minute design changes. However, even hierarchical flows using the current-generation of physical implementation tools are facing problems closing the chip requirement within aggressive schedules. In this paper, we review chip assembly challenges and discuss the requirements of an implementation system that comprehensively addresses all the issues.
Critical Feature Analysis as Golden Path to DFM Closure
This paper discusses the features implemented in a Design for Manufacturability (DFM) checker for Critical Feature Analysis of Very Deep Sub-Micron (VDSM) layout designs. This checker leverages Calibre® Yield Analyzer (YA) and Yield Enhancer (YE) functionality, as well as Calibre TCL Verification Format. A central feature of the deck is the identification of opportunities where a layout situation can be improved in a simple, straightforward manner without increasing area inside the top cell boundary. The purpose of such optimization is to increase design robustness to systematic and random yield loss mechanisms and reliability issues without increasing silicon area and cost. An overview of the improvability algorithms implemented using YE features is described, with focus on specific examples of macro code and improvability results on real-life layout cases. Also presented is the use of YA functionality to quantify the gain possible from the application of identified improvements in terms of DFM score. The benefit of this feedback is that it helps designers in prioritizing and selecting the layout improvements to make. Application of the proposed layout optimization flow is finally demonstrated on a 90nm SRAM memory cut design for automotive applications.
Calibre OTSS Validation for Medical Applications
This paper provides an overview of Calibre Off-The-Shelf Software (OTSS) validation required by the Food and Drug Administration (FDA) for implantable medical devices. It is based on a Mentor Graphics (MGC) generated Calibre Quality Assurance (QA) document combined with internal Calibre® DRC/LVS in-house testing performed at Boston Scientific (BSC). The following Calibre QA issues will be emphasized first: product lifecycle models, release risk management and monitoring, defect classification, tracking and reporting, functional validation and regression testing, quality metrics. Following the Calibre QA introduction, it will cover these specific topics: project setup, performing Calibre DRC, LVS and XOR tests, regression suite and final results verification scripting, and correlation of vendor assessment of quality versus internal testing outcomes to complete OTSS Calibre validation.
Reducing IC Cycle Time with Calibre
Technology is both a blessing and a curse. The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is also responsible for the significant increases we have seen in the number and complexity of verification rules. It would be nice if we could use this phenomenon to our advantage, as an excuse for why our job of physical verification should take longer and why we should be given more time than we had for our previous project. As nice as that would be, this is not the case. Increasing competitive environments and the always present compulsion to get products out to market in a timely manner have not permitted such luxuries. Fortunately, despite conspiring forces to elongate this already difficult task, there is a light at the end of the tunnel (no, not a train coming the other direction), the Calibre suite of verification tools, specifically Calibre nmDRC, Calibre nmLVS and Calibre Incremental DRC.
Reducing Physical Verification Cycle Time
As a result, ensuring that the original design intent is maintained is increasingly difficult. Identifying these new defect mechanisms puts a new burden on physical verification runtimes. Worse still, due to the complexity of these effects, debugging a problem through layout modifications without generating some new problem is more challenging, requiring more verification iterations than ever before. Given these impacts, the time required to iterate from design to a physically- and electrically-clean layout in these designs can rapidly overrun production schedules and delivery dates.
Clearly, new verification strategies are needed. All aspects of the physical verification cycle, from physical verification run times to the time required to identify, understand and debug design violations, must be re-evaluated. Engineers must be able to identify new complex physical interactions and characterize all physical, topological and electrical failure mechanisms associated with new process. Maintaining real-world production schedules, however, means increasing the number of iterations required to validate fixes while decreasing the total runtimes for each component. Design violations must be presented as clearly and efficiently as possible, to reduce debugging time, and approaches that reduce the time required to re-verify the impact of changes to a design must be implemented.
Calibre provides the most comprehensive and forward-looking functionality for performing DRC, LVS and DFM simulations. Through hyperscaling technology and the ability to utilize specialized cell processor architecture, Calibre ensures the fastest possible runtimes. The advanced debugging features of Calibre RVE presents all failure mechanisms to the user in a simple interface, directly within the engineer's design environment. With incremental verification and debug, Calibre lets engineers validate the impacts of design modifications without waiting for DRC runs to complete. Together, these capabilities offer the ability to dramatically reduce the total physical verification cycle time.
Implementation-Quality Prototyping With Olympus-SoCTM: Accelerating Design Closure for Advanced ICs
Confronting Chip Assembly Challenges: Avoid Late-Stage Bottlenecks in Physical Design
At nanometer technologies, IC physical design teams are designing multi-million gate products with very complex functionality including different processor cores, memory blocks, and analog circuitry on a single chip. In addition to addressing the sheer size and complexity, designers also need to deal with variations in design modes, environmental conditions, manufacturing steps, and device and interconnect behavior. In recent years, hierarchical approaches have gained traction for the implementation of multi-million gate SOCs. However, at these design sizes, flows using the current-generation of physical implementation severely strained to meet the chip specifications with aggressive schedules.
Using Mentor Graphics Automated Routing Tools in an Analog Layout Flow
Analog layout practices, whether cmos or bipolar, have gone generally unchanged for many years. Now, Mentor Graphics' ICFlow tools including the SDL flow along with the ARoute and IRoute tools enables analog layout designers to better utilize their skills while shifting some of the more mundane layout tasks to the tools. With analog content in ASIC designs increasing and more analog functionality being put into silicon all of the time, the time interval to production is shortening and the need for a more efficient and expedient tool-based solution becomes apparent.
Most analog / mixed signal physical design flows fail to take advantage of current tool suite offerings with respect to automation. Whether due to inexperience or analog design reticence to pursue more modern techniques, today's analog design environment would greatly benefit from even incremental adoption of automation.
This paper describes a methodology for using a mixture of schematic, manually created and assigned layout along with viewpoint properties to allow the IRoute and ARoute tools to perform in a more analog-friendly mode. The mixture of techniques described can be implemented in whole as part of a comprehensive SDL / ECO analog design and layout flow, or more likely in piecemeal fashion as part of an incremental technique adoption.