Technical Papers
The Need for Advanced Silicon Modeling in RF Nanometer Designs
Chip IR Drop Reduction Through Automated Via Checking and Addition
Complex physical designs (layouts) in 65 nm and below process nodes often use ten (10) or more layers of metallization. So, the length of supply (power/ground) nets as well as that of clock and signal nets is typically long, and the nets involve multiple layers of Vias. These Vias tend to dominate the impedance due to these nets. It is, therefore, often the case that insufficient Via placements on the junctions between Metal(N) and Metal(N+1) turns out to be the root cause of the IR drop failures, and net delays giving rise to setup and hold time violations. The other detrimental effect of Via-deficient junctions is increased heat dissipation and current crowding leading to electro-migration. Wide metals warping resulting in unreliable Via connections require redundant Via placements. Some Via-deficient junctions may barely meet redundant Via requirements, but additional Vias often make the junctions more robust. This paper discusses a simple Perl-Calibre® approach to check for and add Vias to M(N)-M(N+1) junctions that have insufficient Vias or no Vias, but could hold more Vias without violating the topological design rules checks (DRCs). The Vias are checked for and added to junctions on user-specified nets. Although, typically supply nets (VDD,VSS) are handled by the code, there are actually no restrictions on the net names as long as they are top-level net names that can be traced downwards along metal and via lines, or even other connectivity layers.
Calibre Rule Code Testability: The Good, The Bad, and The Ugly
Writing Calibre® rule checks is easy. Writing correct, complete, and efficient checks, however, takes more effort. A well-defined business process for software development is a must to ensure good rule sets. This paper focuses on testability and test development as critical components of this process. It also provides an overview of robust SVRF development practices from understanding the intent of the rule, test case development, code development, code reviews, and maintenance of test cases, documentation, and code for the life of the process node. This paper provides tips and tricks to efficiently develop cases to validate that a rule set checks exactly the required rules, with proper handling of corner cases, to prevent the costly mistakes of false errors or missed real errors. It shares practices wherein a good set of test cases and well-developed plan can help transform code from bad or ugly to good.
An Evolution of Gate and Via Parasitic Resistance Extraction
Cypress has recently modified the parasitic resistance extraction of Vias and Gates. Rather than use a hard number for PEX VIA REDUCTION COUNT for Via grouping, we have found that using FLEXIBLE PEX VIA REDUCTION RESISTANCE for all layers and allowing user specified application of the "STANDARD COUNT" modifier provides nodal reduction and the ability to increase accuracy if needed. For transistor devices, Cypress extracts parasitic resistance to the center of the seed layer, one half the width of gate. Gates only contacted on one side omit one half of the resistance. Experiments have shown that a more accurate estimation is one third. To achieve that accuracy, our flow now uses RESISTANCE DEVICE_SEED to lower poly resistance. Capacitive accuracy is maintained by treating the gate device as poly a equivalent through the use of CAPACITANCE ALIAS. This paper presents details on the evolution of our parasitic resistance flow.
Computation of parasitic capacitances of an IC cell in accounting for photolithography effect
Further Reducing the High Cost of Processing Power
processing of design data an essential part of design-to-silicon flows.
To achieve profitability, design houses and fabs alike must be able to
process huge and complicated volumes of design data swiftly. Turn around
time (TAT) must be held to a minimum to ensure that designs are readied
for manufacturing as quickly as possible in order to keep costs low and
take advantage of volatile windows of opportunity in the marketplace.
With Calibre(r) MT or MTflex, TAT is reduced and throughput is
increased. For large IDMs or foundries that must process several jobs,
hardware configurations can be better utilized to optimize the total
number of jobs that can run through in any given day.
A Fully Automated Approach for Analog Circuit Reuse
Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It is not based on any optimization techniques, but rather relies on a new algorithm based on knowledge extraction, which makes it a very fast technique. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics, symmetry) and then produces a re-sized design in the target technology with the same performance as the original design. The migration of a low voltage Delta Sigma modulator is presented in this paper to validate the migration engine.