Technical Papers
The Platform Solution: Leveraging Calibre's Power of Integrated, High Performance Tools
Implementation-Quality Prototyping With Olympus-SoCTM: Accelerating Design Closure for Advanced ICs
The growing complexity of today’s ICs and tight market schedules are driving a demand for more powerful solutions for design prototyping. Prototyping helps designers determine the feasibility of implementing a particular design given the various requirements. By using Olympus-SoC for rapid prototyping early in the design cycle, designers can catch issues with macro placement, missing constraints, RTL problems, and many other design problems. In this paper, we show how design prototyping with the Mentor Graphics Olympus-SoC physical implementation system improves predictability and facilitates design closure.
Confronting Chip Assembly Challenges: Avoid Late-Stage Bottlenecks in Physical Design
The increasing size and complexity of today’s multi-million gate SoCs necessitates hierarchical chip design methodologies, which partition the chip into smaller pieces. A hierarchical methodology is necessary for large SoCs because it extends the capacity of design-automation tools, improves tool runtimes, and limits last minute design changes. However, even hierarchical flows using the current-generation of physical implementation tools are facing problems closing the chip requirement within aggressive schedules. In this paper, we review chip assembly challenges and discuss the requirements of an implementation system that comprehensively addresses all the issues.
Design for Variability: Managing Design, Process, and Manufacturing Variations in Physical Design
At nanometer technologies, variability has become one of the leading causes for chip failures and delayed schedules. For nanometer design implementation flows, variability is associated with design modes, power states, environmental conditions, manufacturing steps, and the behavior of devices and interconnects. Variability affects the entire physical design environment, from power management, through timing and signal integrity closure, to manufacturability.
This paper explores the different forms of variability, reviews the challenges involved in modeling variability, and discusses the requirements of an implementation system that comprehensively analyzes and optimizes a design for best results in the presence of variability.
Implementation-Quality Prototyping With Olympus-SoCTM: Accelerating Design Closure for Advanced ICs
Confronting Chip Assembly Challenges: Avoid Late-Stage Bottlenecks in Physical Design
At nanometer technologies, IC physical design teams are designing multi-million gate products with very complex functionality including different processor cores, memory blocks, and analog circuitry on a single chip. In addition to addressing the sheer size and complexity, designers also need to deal with variations in design modes, environmental conditions, manufacturing steps, and device and interconnect behavior. In recent years, hierarchical approaches have gained traction for the implementation of multi-million gate SOCs. However, at these design sizes, flows using the current-generation of physical implementation severely strained to meet the chip specifications with aggressive schedules.
Further Reducing the High Cost of Processing Power
processing of design data an essential part of design-to-silicon flows.
To achieve profitability, design houses and fabs alike must be able to
process huge and complicated volumes of design data swiftly. Turn around
time (TAT) must be held to a minimum to ensure that designs are readied
for manufacturing as quickly as possible in order to keep costs low and
take advantage of volatile windows of opportunity in the marketplace.
With Calibre(r) MT or MTflex, TAT is reduced and throughput is
increased. For large IDMs or foundries that must process several jobs,
hardware configurations can be better utilized to optimize the total
number of jobs that can run through in any given day.
A Fully Automated Approach for Analog Circuit Reuse
Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It is not based on any optimization techniques, but rather relies on a new algorithm based on knowledge extraction, which makes it a very fast technique. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics, symmetry) and then produces a re-sized design in the target technology with the same performance as the original design. The migration of a low voltage Delta Sigma modulator is presented in this paper to validate the migration engine.